I have been wondering: should we allow live migration with the
invtsc flag enabled, if TSC scaling is available on the

For reference, this is what the Intel SDM says about invtsc:

  The time stamp counter in newer processors may support an
  enhancement, referred to as invariant TSC. Processor’s support
  for invariant TSC is indicated by CPUID.80000007H:EDX[8].

  The invariant TSC will run at a constant rate in all ACPI P-,
  C-. and T-states. This is the architectural behavior moving
  forward. On processors with invariant TSC support, the OS may
  use the TSC for wall clock timer services (instead of ACPI or
  HPET timers). TSC reads are much more efficient and do not
  incur the overhead associated with a ring transition or access
  to a platform resource.


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