On Mon, Jan 09, 2017 at 04:05:08PM +0000, Peter Maydell wrote:
> Augment the GIC's QOM device interface by adding two
> new sets of sysbus IRQ lines, to signal VIRQ and VFIQ to
> each CPU.
>
> We never use these, but it's helpful to keep the v2-and-earlier
> GIC's external interface in line with that of the GICv3 to
> avoid board code having to add extra code conditional on which
> version of the GIC is in use.
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> ---
> include/hw/intc/arm_gic_common.h | 2 ++
> hw/intc/arm_gic_common.c | 6 ++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/include/hw/intc/arm_gic_common.h
> b/include/hw/intc/arm_gic_common.h
> index f4c349a..af3ca18 100644
> --- a/include/hw/intc/arm_gic_common.h
> +++ b/include/hw/intc/arm_gic_common.h
> @@ -55,6 +55,8 @@ typedef struct GICState {
>
> qemu_irq parent_irq[GIC_NCPU];
> qemu_irq parent_fiq[GIC_NCPU];
> + qemu_irq parent_virq[GIC_NCPU];
> + qemu_irq parent_vfiq[GIC_NCPU];
> /* GICD_CTLR; for a GIC with the security extensions the NS banked
> version
> * of this register is just an alias of bit 1 of the S banked version.
> */
> diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
> index 0a1f56a..4a8df44 100644
> --- a/hw/intc/arm_gic_common.c
> +++ b/hw/intc/arm_gic_common.c
> @@ -110,6 +110,12 @@ void gic_init_irqs_and_mmio(GICState *s,
> qemu_irq_handler handler,
> for (i = 0; i < s->num_cpu; i++) {
> sysbus_init_irq(sbd, &s->parent_fiq[i]);
> }
> + for (i = 0; i < s->num_cpu; i++) {
> + sysbus_init_irq(sbd, &s->parent_virq[i]);
> + }
> + for (i = 0; i < s->num_cpu; i++) {
> + sysbus_init_irq(sbd, &s->parent_vfiq[i]);
> + }
>
> /* Distributor */
> memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
> --
> 2.7.4
>
