On Mon, Jan 9, 2017 at 8:05 AM, Peter Maydell <peter.mayd...@linaro.org> wrote:
> The GICv3 support for virtualization includes an outbound
> maintenance interrupt signal which is asserted when the
> CPU interface wants to signal to the hypervisor that it
> needs attention. Expose this as an outbound GPIO line from
> the CPU object which can be wired up as a physical interrupt
> line by the board code (as we do already for the CPU timers).
>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Reviewed-by: Alistair Francis <alistair.fran...@xilinx.com>
Thanks,
Alistair
> ---
> target/arm/cpu.h | 2 ++
> target/arm/cpu.c | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index ab119e6..764b511 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -555,6 +555,8 @@ struct ARMCPU {
> QEMUTimer *gt_timer[NUM_GTIMERS];
> /* GPIO outputs for generic timer */
> qemu_irq gt_timer_outputs[NUM_GTIMERS];
> + /* GPIO output for GICv3 maintenance interrupt signal */
> + qemu_irq gicv3_maintenance_interrupt;
>
> /* MemoryRegion to use for secure physical accesses */
> MemoryRegion *secure_memory;
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index f5cb30a..8932086 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -466,6 +466,9 @@ static void arm_cpu_initfn(Object *obj)
> arm_gt_stimer_cb, cpu);
> qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
> ARRAY_SIZE(cpu->gt_timer_outputs));
> +
> + qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
> + "gicv3-maintenance-interrupt", 1);
> #endif
>
> /* DTB consumers generally don't in fact care what the 'compatible'
> --
> 2.7.4
>
>
