On 23 January 2018 at 03:53, Richard Henderson <richard.hender...@linaro.org> wrote: > Add both SVE exception state and vector length. > > Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c > index 10eef870fe..4c1eca7062 100644 > --- a/target/arm/translate-a64.c > +++ b/target/arm/translate-a64.c > @@ -11263,6 +11263,8 @@ static int > aarch64_tr_init_disas_context(DisasContextBase *dcbase, > dc->user = (dc->current_el == 0); > #endif > dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); > + dc->sve_excp_el = ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags); > + dc->sve_len = (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16; You've carefully arranged that the sve_excp checks are a superset of the fp_excp checks, which means that we get the correct exception prioritization by always doing the sve_excp check first and then the fp_excp check second, without having to look at whether fp_excp_el or sve_excp_el is larger to see which should take precedence. We could assert(dc->sve_excp_el <= dc->fp_excp_el); and perhaps have a comment noting why this is useful... Otherwise Reviewed-by: Peter Maydell <peter.mayd...@linaro.org> thanks -- PMM
