On 02/09/2018 08:58 AM, Peter Maydell wrote:
> Instead of hardcoding the values of M profile ID registers in the
> NVIC, use the fields in the CPU struct. This will allow us to
> give different M profile CPU types different ID register values.
> This commit includes the addition of the missing ID_ISAR5,
> which exists as RES0 in both v7M and v8M.
> (The values of the ID registers might be wrong for the M4 --
> this commit leaves the behaviour there unchanged.)
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
> hw/intc/armv7m_nvic.c | 30 ++++++++++++++++--------------
> target/arm/cpu.c | 28 ++++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>