On 17 April 2018 at 23:49, Richard Henderson <richard.hender...@linaro.org> wrote: > On 04/17/2018 12:38 PM, Emilio G. Cota wrote: >> On Tue, Apr 17, 2018 at 22:45:51 +0100, Peter Maydell wrote: >>> On 17 April 2018 at 22:27, Emilio G. Cota <c...@braap.org> wrote: >>>> (...) >>>> +cff 0xffb00000, expected: 0x7ff8000000000000, returned: >>>> 0x7ff4000000000000, \ >>>> expected exceptions: i, returned: none >>>> +error: flags mismatch for input @ ibm/Basic-Types-Inputs.fptest:26170: >>>> +b32b64cff =0 S -> Q i >>> >>> SNaN conversion from 32 bit to 64 bit. Here I agree >>> with the test -- we should quieten the NaN and raise >>> Invalid -- which implies that the hardware is wrong ?!? >> >> This passes on an Intel host, and fails on both Power7 and 8 hosts I have >> access to. I don't have the Power ISA spec in front of me, but I hope >> there's something about this specified in it. > > IIRC this is unspecified and does vary by implementation.
I think 754-2008 does specify it: s6.2 says that you get 'set Invalid and return a QNaN if an input is an SNaN' for "every general-computational and signaling-computational operation except for the conversions described in 5.12". So the only exceptions are: 1) the s5.12 conversions, which are to/from strings-of-characters 2) quiet-computational operations, which are just copy, abs, negate, copySign, and some re-encoding operations involving decimal formats float-to-float conversions are general-computational. I don't have the original IEEE754 spec to hand though; that may have left this unspecified. thanks -- PMM