On Thu, Apr 19, 2018 at 05:52:23PM +0200, Paolo Bonzini wrote: > On 19/04/2018 17:42, Michael S. Tsirkin wrote: > >> A compiler barrier is enough on strongly-ordered memory platform. > >> As it doesn't re-order store, PCI device won't see a stale index > >> value. But a weakly-ordered memory needs sfence. > > > > Oh you are right. > > > > So it's only needed for non-intel platforms or when packets are in > > WC memory then. And I don't know whether dpdk ever puts packets in WC > > memory. > > > > I guess we'll cross this bridge when we get to it. > > Non-TSO architectures seem important... > > Paolo
Only if there are virtio offload engines on platforms with these architectures :) Worth working on for sure but doesn't have to block this patchset. -- MST
