On 26 April 2018 at 19:18, Thomas Huth <th...@redhat.com> wrote: > I don't think it makes sense to instantiate e.g. an interrupt controller > with the "none" machine automatically ... so the raw cortex-m3 core > should either be usable without that, too
The interrupt controller in an M-profile core is an integral part of the CPU itself (it happens to be accessible via memory-mapped accesses); our "nvic" object in QEMU also implements various other "core part of the CPU but the interface is memory mapped registers" functionality that isn't strictly part of the interrupt controller. A configuration which has an M profile CPU and does not have these registers and the interrupt controller isn't architecturally permitted and is just not right. We shouldn't let users configure QEMU that way. It's not really clear to me what the "none" machine is for, though... > or there just should be an error message instead of a crash > when the additional hardware is not available This would certainly be a good start. (M profile is significantly different from A profile in this area, which is why A profile doesn't crash here.) thanks -- PMM
