Some ARM processors (consider PXA2xx, Omap1, etc.) want to be able to send CPU_INTERRUPT_EXITTB to the cpu. Support doing that through common arm_pic.
Signed-off-by: Dmitry Eremin-Solenikov <dbarysh...@gmail.com> --- hw/arm-misc.h | 1 + hw/arm_pic.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index 010acb4..f2e45ee 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -14,6 +14,7 @@ /* The CPU is also modeled as an interrupt controller. */ #define ARM_PIC_CPU_IRQ 0 #define ARM_PIC_CPU_FIQ 1 +#define ARM_PIC_CPU_WAKE 2 qemu_irq *arm_pic_init_cpu(CPUState *env); /* armv7m.c */ diff --git a/hw/arm_pic.c b/hw/arm_pic.c index f44568c..bd5ce55 100644 --- a/hw/arm_pic.c +++ b/hw/arm_pic.c @@ -38,6 +38,10 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) else cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ); break; + case ARM_PIC_CPU_WAKE: + if (env->halted && level) + cpu_interrupt(env, CPU_INTERRUPT_EXITTB); + break; default: hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq); } @@ -45,5 +49,5 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) qemu_irq *arm_pic_init_cpu(CPUState *env) { - return qemu_allocate_irqs(arm_pic_cpu_handler, env, 2); + return qemu_allocate_irqs(arm_pic_cpu_handler, env, 3); } -- 1.7.2.3