On 12 June 2018 at 21:46, Julia Suvorova <jus...@mail.ru> wrote:
> @@ -10085,10 +10091,25 @@ static void disas_thumb2_insn(DisasContext *s,
> uint32_t insn)
> int conds;
> int logic_cc;
>
> - /* The only 32 bit insn that's allowed for Thumb1 is the combined
> - * BL/BLX prefix and suffix.
> + /*
> + * ARMv6-M supports a limited subset of Thumb2 instructions.
> + * Other Thumb1 architectures allow only 32-bit
> + * combined BL/BLX prefix and suffix.
> */
> - if ((insn & 0xf800e800) != 0xf000e800) {
> + if (arm_dc_feature(s, ARM_FEATURE_M) && arm_dc_feature(s,
> ARM_FEATURE_V6)) {
I realized during testing that this accidentally breaks v7M and v8M,
because those cores define both ARM_FEATURE_V6 and _V7 (and _V8 for v8M),
so this condition is true and we undef on the non-v6M insns for
v7M and v8M too. I've fixed this in target-arm.next by changing the
condition to
+ if (arm_dc_feature(s, ARM_FEATURE_M) &&
+ !arm_dc_feature(s, ARM_FEATURE_V7)) {
thanks
-- PMM
