On Fri, 14 Dec 2018 at 17:26, Alex Bennée <alex.ben...@linaro.org> wrote:
>
>
> Richard Henderson <richard.hender...@linaro.org> writes:
>
> > On 12/13/18 8:55 AM, Alex Bennée wrote:
> >>
> >> Ard Biesheuvel <ard.biesheu...@linaro.org> writes:
> >>
> >>> Hi Alex,
> >>>
> >>> Thanks again for looking into this.
> >>>
> >>> On Thu, 13 Dec 2018 at 12:55, Alex Bennée <alex.ben...@linaro.org> wrote:
> >> <snip>
> >>>
> >>>>
> >>>> int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct
> >>>> kvm_sw_breakpoint *bp)
> >>>> {
> >>>> + CPUARMState *env = &ARM_CPU(cs)->env;
> >>>> + int el = arm_current_el(env);
> >>>> + bool is_aa64 = arm_el_is_aa64(env, el);
> >>>> + const uint32_t *bpi = is_aa64 ? &brk_insn : &bkpt_insn;
> >>>> +
> >>>> if (have_guest_debug) {
> >>>> if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn,
> >>>> 4, 0) ||
> >>>> - cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&brk_insn, 4,
> >>>> 1)) {
> >>>> + cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)bpi, 4, 1)) {
> >>>
> >>> Should we be dealing with endianness here?
> >>>
> >> <snip>
> >>
> >> I don't think so - everything eventually ends up (ld|st)n_p which deals
> >> with the endianness details.
> >
> > I think Ard is right. You need to consider dynamic endianness with
> >
> > bswap_code(arm_sctlr_b(env))
>
> *sigh* I guess. It of course still a heuristic that can break because we
> don't know if the system will have switched mode by the time it gets to
> the breakpoint.
>
Actually, I was referring to the QEMU/host side. Instruction encodings
are always little endian in ARMv7 and v8 (which is all KVM cares about
in any case), but I guess it is [theoretically?] possible that we are
running a BE QEMU?
