Hi, this has just a bunch compile fixes caused by patches 17 and 18. So I only resend these patches.
full tree is available at https://github.com/bkoppelmann/qemu/tree/riscv-dt-v9 Bastian Koppelmann (29): target/riscv: Activate decodetree and implemnt LUI & AUIPC target/riscv: Convert RVXI branch insns to decodetree target/riscv: Convert RV32I load/store insns to decodetree target/riscv: Convert RV64I load/store insns to decodetree target/riscv: Convert RVXI arithmetic insns to decodetree target/riscv: Convert RVXI fence insns to decodetree target/riscv: Convert RVXI csr insns to decodetree target/riscv: Convert RVXM insns to decodetree target/riscv: Convert RV32A insns to decodetree target/riscv: Convert RV64A insns to decodetree target/riscv: Convert RV32F insns to decodetree target/riscv: Convert RV64F insns to decodetree target/riscv: Convert RV32D insns to decodetree target/riscv: Convert RV64D insns to decodetree target/riscv: Convert RV priv insns to decodetree target/riscv: Convert quadrant 0 of RVXC insns to decodetree target/riscv: Convert quadrant 1 of RVXC insns to decodetree target/riscv: Convert quadrant 2 of RVXC insns to decodetree target/riscv: Remove gen_jalr() target/riscv: Remove manual decoding from gen_branch() target/riscv: Remove manual decoding from gen_load() target/riscv: Remove manual decoding from gen_store() target/riscv: Move gen_arith_imm() decoding into trans_* functions target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists target/riscv: Remove shift and slt insn manual decoding target/riscv: Remove manual decoding of RV32/64M insn target/riscv: Rename trans_arith to gen_arith target/riscv: Remove gen_system() target/riscv: Remove decode_RV32_64G() target/riscv/Makefile.objs | 19 + target/riscv/insn16.decode | 129 ++ target/riscv/insn32-64.decode | 72 + target/riscv/insn32.decode | 201 ++ .../riscv/insn_trans/trans_privileged.inc.c | 110 + target/riscv/insn_trans/trans_rva.inc.c | 218 ++ target/riscv/insn_trans/trans_rvc.inc.c | 327 +++ target/riscv/insn_trans/trans_rvd.inc.c | 442 ++++ target/riscv/insn_trans/trans_rvf.inc.c | 439 ++++ target/riscv/insn_trans/trans_rvi.inc.c | 568 +++++ target/riscv/insn_trans/trans_rvm.inc.c | 120 ++ target/riscv/translate.c | 1847 +++-------------- 12 files changed, 2897 insertions(+), 1595 deletions(-) create mode 100644 target/riscv/insn16.decode create mode 100644 target/riscv/insn32-64.decode create mode 100644 target/riscv/insn32.decode create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c create mode 100644 target/riscv/insn_trans/trans_rva.inc.c create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c -- 2.21.0
