On 3/23/19 2:10 AM, Howard Spoelstra wrote: > I applied this series to master on a G5 and a G4, both with Lubuntu. The > qemu-system-ppc and qemu-system-ppc64 builds fail to run on both. Below is the > gdb output from running a debug-enabled qemu-system-ppc on the G5.
Please try the following, which should fix that assert. I have also updated by branch: https://github.com/rth7680/qemu/tree/tcg-ppc-vsx r~ --- >From ca448a66e2596131aa7a30a16230676d3ef77b9c Mon Sep 17 00:00:00 2001 From: Richard Henderson <richard.hender...@linaro.org> Date: Sat, 23 Mar 2019 19:40:05 +0000 Subject: [PATCH] tcg/ppc: Support vector dup2 This is only used for 32-bit hosts. Signed-off-by: Richard Henderson <richard.hender...@linaro.org> --- tcg/ppc/tcg-target.inc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 4373989..00106f3 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -3114,6 +3114,14 @@ static void tcg_out_vec_op } break; + case INDEX_op_dup2_vec: + assert(TCG_TARGET_REG_BITS == 32); + /* With inputs a1 = xLxx, a2 = xHxx */ + tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ + tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ + tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ + return; + case INDEX_op_ppc_mrgh_vec: insn = mrgh_op[vece]; break; @@ -3492,6 +3500,7 @@ static const TCGTargetOpDef *tcg_target_op_def case INDEX_op_ppc_mulou_vec: case INDEX_op_ppc_pkum_vec: case INDEX_op_ppc_rotl_vec: + case INDEX_op_dup2_vec: return &v_v_v; case INDEX_op_not_vec: case INDEX_op_dup_vec: -- 1.8.3.1
