To avoid incoherent states when the machine resets (see but report below), add the device reset callback.
A "system reset" sets the device state machine in READ_ARRAY mode and, after some delay, set the SR.7 READY bit. Since we do not model timings, we set the SR.7 bit directly. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1678713 Reported-by: Laszlo Ersek <ler...@redhat.com> Reviewed-by: John Snow <js...@redhat.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <phi...@redhat.com> --- hw/block/pflash_cfi01.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 435be1e35c..a1ec1faae5 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -865,6 +865,24 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ } +static void pflash_cfi01_system_reset(DeviceState *dev) +{ + PFlashCFI01 *pfl = PFLASH_CFI01(dev); + + /* + * The command 0x00 is not assigned by the CFI open standard, + * but QEMU historically uses it for the READ_ARRAY command (0xff). + */ + pfl->cmd = 0x00; + pfl->wcycle = 0; + memory_region_rom_device_set_romd(&pfl->mem, true); + /* + * The WSM ready timer occurs at most 150ns after system reset. + * This model deliberately ignores this delay. + */ + pfl->status = 0x80; +} + static Property pflash_cfi01_properties[] = { DEFINE_PROP_DRIVE("drive", PFlashCFI01, blk), /* num-blocks is the number of blocks actually visible to the guest, @@ -909,6 +927,7 @@ static void pflash_cfi01_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + dc->reset = pflash_cfi01_system_reset; dc->realize = pflash_cfi01_realize; dc->props = pflash_cfi01_properties; dc->vmsd = &vmstate_pflash; -- 2.20.1
