On 8/1/19 4:38 PM, Peter Maydell wrote: > On Thu, 1 Aug 2019 at 15:20, Damien Hedde <[email protected]> wrote: >> >> >> On 8/1/19 12:57 PM, Peter Maydell wrote: >>> In Arm v8.0 M-profile CPUs without the Security Extension and also in >>> v7M CPUs, there is no NSACR register. However, the code we have to handle >>> the FPU does not always check whether the ARM_FEATURE_M_SECURITY bit >>> is set before testing whether env->v7m.nsacr permits access to the >>> FPU. This means that for a CPU with an FPU but without the Security >>> Extension we would always take a bogus fault when trying to stack >>> the FPU registers on an exception entry. >>> >>> We could fix this by adding extra feature bit checks for all uses, >>> but it is simpler to just make the internal value of nsacr 0x3ff >> >> s/0x3ff/0xcff/ I think, given you put 0xcff after and in the code > > Yes, 0xcff is correct and the commit message is wrong. (Bits 8 and 9 > of the NSACR are RES0 in all situations.) >
Reviewed-by: Damien Hedde <[email protected]>
