The previous version can be found at [1]. Changes compared to v2:
- Expanded the instruction operand infrastructure a bit; I am now
fairly confident that it is powerful enough to accommodate for all
the use cases I will need. It's still a bit clunky to work with at
times, but I am happy with it for now.
- Reduced the number of various INSN_* (now called OPCODE_*) macro
variants using variadic macros.
- Implemented translation for instructions up to SSE3.
Cheers,
-Jan
References:
1. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg01790.html
Jan Bobek (43):
target/i386: reduce scope of variable aflag
target/i386: use dflag from DisasContext
target/i386: use prefix from DisasContext
target/i386: use pc_start from DisasContext
target/i386: make variable b1 const
target/i386: make variable is_xmm const
target/i386: add vector register file alignment constraints
target/i386: introduce gen_(ld,st)d_env_A0
target/i386: introduce gen_sse_ng
target/i386: disable unused function warning temporarily
target/i386: introduce mnemonic aliases for several gvec operations
target/i386: introduce function ck_cpuid
target/i386: introduce instruction operand infrastructure
target/i386: introduce generic operand alias
target/i386: introduce generic either-or operand
target/i386: introduce generic load-store operand
target/i386: introduce tcg_temp operands
target/i386: introduce modrm operand
target/i386: introduce operands for decoding modrm fields
target/i386: introduce operand for direct-only r/m field
target/i386: introduce operand vex_v
target/i386: introduce Ib (immediate) operand
target/i386: introduce M* (memptr) operands
target/i386: introduce G*, R*, E* (general register) operands
target/i386: introduce P*, N*, Q* (MMX) operands
target/i386: introduce H*, V*, U*, W* (SSE/AVX) operands
target/i386: introduce code generators
target/i386: introduce helper-based code generator macros
target/i386: introduce gvec-based code generator macros
target/i386: introduce sse-opcode.inc.h
target/i386: introduce instruction translator macros
target/i386: introduce MMX translators
target/i386: introduce MMX code generators
target/i386: introduce MMX instructions to sse-opcode.inc.h
target/i386: introduce SSE translators
target/i386: introduce SSE code generators
target/i386: introduce SSE instructions to sse-opcode.inc.h
target/i386: introduce SSE2 translators
target/i386: introduce SSE2 code generators
target/i386: introduce SSE2 instructions to sse-opcode.inc.h
target/i386: introduce SSE3 translators
target/i386: introduce SSE3 code generators
target/i386: introduce SSE3 instructions to sse-opcode.inc.h
Richard Henderson (3):
target/i386: Push rex_r into DisasContext
target/i386: Push rex_w into DisasContext
target/i386: Simplify gen_exception arguments
target/i386/cpu.h | 6 +-
target/i386/sse-opcode.inc.h | 699 +++++++++
target/i386/translate.c | 2808 ++++++++++++++++++++++++++++++----
3 files changed, 3189 insertions(+), 324 deletions(-)
create mode 100644 target/i386/sse-opcode.inc.h
--
2.20.1
