On 12/16/19 12:27 AM, Niek Linnenbank wrote:
On Fri, Dec 13, 2019 at 1:09 AM Philippe Mathieu-Daudé
<phi...@redhat.com <mailto:phi...@redhat.com>> wrote:
On 12/2/19 10:09 PM, Niek Linnenbank wrote:
[...]
> +static const MemoryRegionOps allwinner_h3_syscon_ops = {
> + .read = allwinner_h3_syscon_read,
> + .write = allwinner_h3_syscon_write,
> + .endianness = DEVICE_NATIVE_ENDIAN,
> + .valid = {
> + .min_access_size = 4,
> + .max_access_size = 4,
Can you point me to the datasheet page that says this region is
restricted to 32-bit accesses? Maybe you want .valid -> .impl instead?
Hehe well here I can only give the same answer as for the SD/MMC driver:
the datasheet
only provides the base address and register offsets, but nothing
explicitely mentioned about alignment.
I do see that also for this device the registers are 32-bit aligned.
Does that mean I should change MemoryRegionOps to . impl instead?
No, keep them, but add ".impl.min_access_size = 4" (see answer to SD/MMC
model patch).
