On Tue, 18 Feb 2020 at 19:10, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> This bit traps EL1 access to cache maintenance insns that operate
> to the point of unification. There are no longer any references to
> plain aa64_cacheop_access, so remove it.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/arm/helper.c | 53 +++++++++++++++++++++++++++------------------
> 1 file changed, 32 insertions(+), 21 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index ed34d4200f..21ee9cf7de 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -4301,19 +4301,6 @@ static const ARMCPRegInfo uao_reginfo = {
> .readfn = aa64_uao_read, .writefn = aa64_uao_write
> };
>
> -static CPAccessResult aa64_cacheop_access(CPUARMState *env,
> - const ARMCPRegInfo *ri,
> - bool isread)
> -{
> - /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
> - * SCTLR_EL1.UCI is set.
> - */
> - if (arm_current_el(env) == 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) {
> - return CP_ACCESS_TRAP;
> - }
> - return CP_ACCESS_OK;
> -}
> -
> static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env,
> const ARMCPRegInfo *ri,
> bool isread)
> @@ -4336,6 +4323,28 @@ static CPAccessResult
> aa64_cacheop_poc_access(CPUARMState *env,
> return CP_ACCESS_OK;
> }
>
> +static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env,
> + const ARMCPRegInfo *ri,
> + bool isread)
> +{
> + /* Cache invalidate/clean to Point of Unification... */
> + switch (arm_current_el(env)) {
> + case 0:
> + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */
> + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) {
> + return CP_ACCESS_TRAP;
> + }
> + break;
Again, we want to fall through here rather than breaking.
> + case 1:
> + /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */
> + if (arm_hcr_el2_eff(env) & HCR_TPU) {
> + return CP_ACCESS_TRAP_EL2;
> + }
> + break;
> + }
> + return CP_ACCESS_OK;
> +}
thanks
-- PMM
