On 2/27/20 6:24 PM, Robert Hoo wrote:
> if ((bv & 6) == 6 && (b & bit_AVX2)) {
> cache |= CACHE_AVX2;
> }
> + if ((bv & 6) == 6 && (b & bit_AVX512F)) {
> + cache |= CACHE_AVX512F;
> + }
Oh, one more thing I missed -- we have to ensure that the 512-bit registers are
enabled. I believe the minimum is bits 6 and 7 enabled (ZMM_Hi256, Hi16_ZMM),
since we don't know that the compiler won't allocate registers from zmm16-31.
So: (bv & 0xc6) == 0xc6.
You'd be right that some comments would be helpful on these lines. :-P
With that,
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
