Thank you for bug fix. I found trn1, trn2, zip1, zip2, uz1, uz2 instructions seem to have same bug.
-- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1863247 Title: AArch64 EXT instruction for V register does not clear MSB side bits Status in QEMU: Fix Committed Bug description: On AArch64 CPU with SVE register, there seems to be a bug in the operation when executing EXT instruction to V registers. Bits above the 128 bits of the SVE register must be cleared to 0, but qemu- aarch64 seems to hold the value. Example ext v0.16b, v1.16b v2.16b, 8 After executing above instruction, (N-1) to 128 bits of z0 register must be 0, where N is SVE register width. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1863247/+subscriptions
