Signed-off-by: Stephen Long <stepl...@quicinc.com>
---
target/arm/cpu.h | 5 +++++
target/arm/helper-sve.h | 4 ++++
target/arm/sve.decode | 6 ++++++
target/arm/sve_helper.c | 11 +++++++++++
target/arm/translate-sve.c | 16 ++++++++++++++++
5 files changed, 42 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d41c4a08c0..8b1dc38b9c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3880,6 +3880,11 @@ static inline bool isar_feature_aa64_sve2_f64mm(const
ARMISARegisters *id)
return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, F64MM) != 0;
}
+static inline bool isar_feature_aa64_sve2_sm4(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SM4) != 0;
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
index 340fe07801..6cd6fdfae1 100644
--- a/target/arm/helper-sve.h
+++ b/target/arm/helper-sve.h
@@ -2693,3 +2693,7 @@ DEF_HELPER_FLAGS_6(fmmla_d, TCG_CALL_NO_RWG, void, ptr,
ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve2_aesimc, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
+DEF_HELPER_FLAGS_3(sve2_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(sve2_aesd, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(sve2_sm4e, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index f58eb04d11..1cb5792bb1 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -98,6 +98,7 @@
# Two operand with unused vector element size
@pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
+@pd5_pn5_e0 ........ ........ ...... rn:5 rd:5 &rr_esz esz=0
# Two operand
@pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
@@ -1429,3 +1430,8 @@ STNT1_zprz 1110010 .. 10 ..... 001 ... ..... ..... \
## SVE2 crypto unary operations
AESMC 01000101 00 10000011100 0 00000 ..... @rdn_e0
AESIMC 01000101 00 10000011100 1 00000 ..... @rdn_e0
+
+## SVE2 crpyto destructive binary operations
+AESE 01000101 00 10001 0 11100 0 ..... ..... @pd5_pn5_e0
+AESD 01000101 00 10001 0 11100 1 ..... ..... @pd5_pn5_e0
+SM4E 01000101 00 10001 1 11100 0 ..... ..... @pd5_pn5_e0
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
index 5c3dee048d..4204659276 100644
--- a/target/arm/sve_helper.c
+++ b/target/arm/sve_helper.c
@@ -7530,4 +7530,15 @@ void HELPER(NAME)(void *vd, void *vn, uint32_t desc)
\
DO_SVE2_AES_CRYPTO(sve2_aesmc, crypto_aesmc);
DO_SVE2_AES_CRYPTO(sve2_aesimc, crypto_aesmc);
+DO_SVE2_AES_CRYPTO(sve2_aese, crypto_aese);
+DO_SVE2_AES_CRYPTO(sve2_aesd, crypto_aese);
+
#undef DO_SVE2_AES_CRYPTO
+
+void HELPER(sve2_sm4e)(void *vd, void *vn, uint32_t desc)
+{
+ intptr_t i, opr_sz = simd_oprsz(desc);
+ for (i = 0; i < opr_sz; i += 16) {
+ HELPER(crypto_sm4e)(vd + i, vn + i);
+ }
+}
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index f70b7f44e3..6b26d8c512 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -7974,3 +7974,19 @@ static bool trans_##NAME(DisasContext *s, arg_rr_esz *a)
\
DO_SVE2_AES_CRYPTO(AESMC, aesmc, 0)
DO_SVE2_AES_CRYPTO(AESIMC, aesimc, 1)
+DO_SVE2_AES_CRYPTO(AESE, aese, 0)
+DO_SVE2_AES_CRYPTO(AESD, aesd, 1)
+
+static bool trans_SM4E(DisasContext *s, arg_rr_esz *a)
+{
+ if (!dc_isar_feature(aa64_sve2_sm4, s)) {
+ return false;
+ }
+ if (sve_access_check(s)) {
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_2_ool(vec_full_reg_offset(s, a->rd),
+ vec_full_reg_offset(s, a->rn),
+ vsz, vsz, 0, gen_helper_sve2_sm4e);
+ }
+ return true;
+}
--
2.17.1
