On Thu, Jun 18, 2020 at 1:03 AM Bin Meng <bmeng...@gmail.com> wrote: > > On Wed, Jun 17, 2020 at 3:30 AM Atish Patra <atish.pa...@wdc.com> wrote: > > > > Currently, all riscv machines have identical reset vector code > > implementations with memory addresses being different for all machines. > > They can be easily combined into a single function in common code. > > > > Move it to common function and let all the machines use the common function. > > > > Signed-off-by: Atish Patra <atish.pa...@wdc.com> > > --- > > hw/riscv/boot.c | 46 +++++++++++++++++++++++++++++++++++++++++ > > hw/riscv/sifive_u.c | 38 +++------------------------------- > > sifive_u's reset vector has to be different to emulate the real > hardware MSEL pin state. > Please rebase this on top of the following series: > http://patchwork.ozlabs.org/project/qemu-devel/list/?series=183567 > Sure. I will rebase. I think sifive_u may be used in future to emulate other sifive boards in future. This may require additional data in rom. That's why, it's better to keep the reset vector code in sifive_u and just unify spike & virt.
> > hw/riscv/spike.c | 38 +++------------------------------- > > hw/riscv/virt.c | 37 +++------------------------------ > > include/hw/riscv/boot.h | 2 ++ > > 5 files changed, 57 insertions(+), 104 deletions(-) > > > > Regards, > Bin > -- Regards, Atish
