On Fri, 19 Jun 2020 at 18:07, Alistair Francis <alistair.fran...@wdc.com> wrote: > > The following changes since commit 4d285821c5055ed68a6f6b7693fd11a06a1aa426: > > Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into > staging (2020-06-19 11:44:03 +0100) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200619-3 > > for you to fetch changes up to 3eaea6eb4e534f7b87c6eca808149bb671976800: > > hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-19 > 08:25:27 -0700) > > ---------------------------------------------------------------- > This is a range of patches for RISC-V. > > Some key points are: > - Generalise the CPU init functions > - Support the SiFive revB machine > - Improvements to the Hypervisor implementation and error checking > - Connect some OpenTitan devices > - Changes to the sifive_u machine to support U-boot > > v2: > - Fix missing realise assert > > ----------------------------------------------------------------
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1 for any user-visible changes. -- PMM
