On Thu, Jun 25, 2020 at 12:31:49PM +0200, Paolo Bonzini wrote:
> On 25/06/20 00:58, Roman Bolshakov wrote:
> > + uint64_t pdpte[4] = {0, 0, 0, 0};
> > + int i;
> > +
> > + /* Reset IA-32e mode guest (LMA) */
> > + wvmcs(cpu->hvf_fd, VMCS_ENTRY_CTLS, 0);
> > +
>
> Where is the place (if any...) that calls macvm_set_cr0 and
> macvm_set_cr4 from cpu_synchronize_*? If you have such a place it
> should take care of resetting LMA as well. Assuming that no entry
> controls are ever set is quite fragile.
>
Hi Paolo,
Yes, there's such a place. post-init and post-reset invoke
hvf_put_registers() and the latter one calls hvf_put_segments().
hvf_put_segments() sets CR4 and CR0 via macvm_set_cr0/macvm_set_cr4
using the CR0/CR4 from env. So, the reset is relying on generic QEMU
CPUX86State now. LMA in EFER is reset there as well.
I don't know any alternative for PDPTE and VMCS Entry Controls in
CPUX86State, that's why I left explicit reset of the VMCS fields in
post-reset.
Is there an outstanding issue I'm missing?
Regards,
Roman
