On 7/23/20 12:13 AM, Frank Chang wrote: > On Thu, Jul 23, 2020 at 3:15 AM Richard Henderson > <richard.hender...@linaro.org > <mailto:richard.hender...@linaro.org>> wrote: > > On 7/22/20 2:15 AM, frank.ch...@sifive.com <mailto:frank.ch...@sifive.com> > wrote: > > From: Frank Chang <frank.ch...@sifive.com > <mailto:frank.ch...@sifive.com>> > > > > For floating-point operations, the scalar can be taken from a scalar > > f register. If FLEN > SEW, the value in the f registers is checked for > > a valid NaN-boxed value, in which case the least-significant SEW bits > > of the f register are used, else the canonical NaN value is used. > > > > Add helper to generate the correspond NaN-boxed value or the SEW-bit > > canonical NaN for floating-point operations. > > > > Signed-off-by: Frank Chang <frank.ch...@sifive.com > <mailto:frank.ch...@sifive.com>> > > --- > > target/riscv/helper.h | 2 ++ > > target/riscv/vector_helper.c | 32 ++++++++++++++++++++++++++++++++ > > 2 files changed, 34 insertions(+) > > The helper can be done inline in two tcg ops. > > Though, really, we need to coordinate with Liu Zhiwei's other patch set > that > also deals with nan-boxing. > > > So, it's better to leverage the codes > at: https://patchew.org/QEMU/20200626205917.4545-1-zhiwei_...@c-sky.com/ > but has to extend for the case of SEW=16?
Yes, or what becomes of that patch set upon revision. r~
