Re: [RFC v2 75/76] target/riscv: gdb: support vector registers for rv64

[Richard Henderson]

On 7/22/20 2:16 AM, frank.ch...@sifive.com wrote:
> +    if (env->misa & RVV) {
> +        /* TODO: support vlen other than 128, 256, 512 bits. */
> +        const char *vector_xml_name = NULL;
> +        switch (cpu->cfg.vlen) {
> +        case 128:
> +            vector_xml_name = "riscv-64bit-vector-128b.xml";
> +            break;
> +        case 256:
> +            vector_xml_name = "riscv-64bit-vector-256b.xml";
> +            break;
> +        case 512:
> +            vector_xml_name = "riscv-64bit-vector-512b.xml";
> +            break;
> +        default:
> +            vector_xml_name = NULL;
> +            break;
> +        }

I guess this is ok as-is, but consider mirroring arm_gen_dynamic_svereg_xml().


r~