On 8/3/20 4:18 AM, Peter Maydell wrote: > Convert the A32 coprocessor instructions to decodetree. > > Note that this corrects an underdecoding: for the 64-bit access case > (MRRC/MCRR) we did not check that bits [24:21] were 0b0010, so we > would incorrectly treat LDC/STC as MRRC/MCRR rather than UNDEFing > them. > > The decodetree versions of these insns assume the coprocessor > is in the range 0..7 or 14..15. This is architecturally sensible > (as per the comments) and OK in practice for QEMU because the only > uses of the ARMCPRegInfo infrastructure we have that aren't > for coprocessors 14 or 15 are the pxa2xx use of coprocessor 6. > We add an assertion to the define_one_arm_cp_reg_with_opaque() > function to catch any accidental future attempts to use it to > define coprocessor registers for invalid coprocessors. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > --- > target/arm/a32.decode | 19 +++++++++++ > target/arm/helper.c | 29 +++++++++++++++++ > target/arm/translate.c | 74 +++++++++++++++++++++++++++++++++++------- > 3 files changed, 111 insertions(+), 11 deletions(-)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org> r~
