On Thu, 1 Oct 2020 at 18:07, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> On ARM, the Top Byte Ignore feature means that only 56 bits of
> the address are significant in the virtual address. We are
> required to give the entire 64-bit address to FAR_ELx on fault,
> which means that we do not "clean" the top byte early in TCG.
>
> This new interface allows us to flush all 256 possible aliases
> for a given page, currently missed by tlb_flush_page*.
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> +static void tlb_flush_page_bits_by_mmuidx_async_1(CPUState *cpu,
> + run_on_cpu_data data)
> +{
> + target_ulong addr_map_bits = (target_ulong) data.target_ptr;
> + target_ulong addr = addr_map_bits & TARGET_PAGE_MASK;
> + uint16_t idxmap = (addr_map_bits & ~TARGET_PAGE_MASK) >> 6;
> + unsigned bits = addr_map_bits & 0x3f;
So this is unpacking...
> + } else if (idxmap <= MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) {
> + run_on_cpu_data data
> + = RUN_ON_CPU_TARGET_PTR(addr | (idxmap << 6) | bits);
...the value that we packed into an integer here...
> + run_on_cpu_data data
> + = RUN_ON_CPU_TARGET_PTR(addr | (idxmap << 6) | bits);
...here...
> + if (idxmap <= MAKE_64BIT_MASK(0, TARGET_PAGE_BITS - 6)) {
> + run_on_cpu_data data
> + = RUN_ON_CPU_TARGET_PTR(addr | (idxmap << 6) | bits);
...and here.
Could we do something to avoid all these hard-coded 6s and
maybe make it a bit clearer that these two operations
are the inverse of each other?
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
