On 10/13/20 6:25 AM, Philippe Mathieu-Daudé wrote: > Yocto developers have expressed interest in running MIPS32 > CPU with custom number of TLB: > https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html > > Help them by making the number of TLB entries a CPU property, > keeping our set of CPU definitions in sync with real hardware.
You mean keeping the 34kf model within qemu in sync, rather than creating a nonsense model that doesn't exist. Question: is this cpu parameter useful for anything else? Because the ideal solution for a CI loop is to use one of the mips cpu models that has the hw page table walker (CP0C3_PW). Having qemu being able to refill the tlb itself is massively faster. We do not currently implement a mips cpu that has the PW. When I downloaded the document set in 2014, I only got the mips64-pra and neglected to get the mips32-pra. So I don't actually know if the PW applies to mips32. I do know that there's nothing in the kernel that ifdefs around it. So: (1) anyone know if the PW incompatible with mips32? (2) if not, was there any mips32 hw built with PW that we could model? (3) if not, would a cpu parameter to force-enable PW for any r2+ cpu be more useful that frobbing the number of tlb entries? r~