Hi Richard, Please forgive my cumbersome mailing agent at work. Please look inline for 'victor>'
________________________________________ From: Richard Henderson <richard.hender...@linaro.org> Sent: Tuesday, October 13, 2020 7:22 PM To: Philippe Mathieu-Daudé; qemu-devel@nongnu.org; Victor Kamensky (kamensky) Cc: Aleksandar Rikalo; Khem Raj; Aleksandar Markovic; Richard Purdie; Aurelien Jarno; Richard Henderson Subject: Re: [RFC PATCH 0/3] target/mips: Make the number of TLB entries a CPU property On 10/13/20 4:11 PM, Richard Henderson wrote: > On 10/13/20 6:25 AM, Philippe Mathieu-Daudé wrote: >> Yocto developers have expressed interest in running MIPS32 >> CPU with custom number of TLB: >> https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html >> >> Help them by making the number of TLB entries a CPU property, >> keeping our set of CPU definitions in sync with real hardware. > > You mean keeping the 34kf model within qemu in sync, rather than creating a > nonsense model that doesn't exist. victor> Question: do current MIPS "generic" qemu cpu models exist for real victor> out there? I agree my choice was not ideal, but it is not that outlandish victor> and IMO somewhat inline with existence of MIPS generic cpu models. > Question: is this cpu parameter useful for anything else? victor> If you are interested here are my testing numbers of how #TLBs impact victor> user land execution time: victor> https://lists.openembedded.org/g/openembedded-core/message/143115 > Because the ideal solution for a CI loop is to use one of the mips cpu models > that has the hw page table walker (CP0C3_PW). Having qemu being able to > refill > the tlb itself is massively faster. > > We do not currently implement a mips cpu that has the PW. When I downloaded Bah, "mips32 cpu". We do have the P5600 that does has it, though the code is wrapped up in TARGET_MIPS64. I'll also note that the code could be better placed [*] > (1) anyone know if the PW incompatible with mips32? I've since found a copy of the mips32-pra in the wayback machine and have answered this as "no" -- PW is documented for mips32. > (2) if not, was there any mips32 hw built with PW > that we could model? But I still don't know about this. A further question for the Yocto folks: could you make use of a 64-bit kernel in testing a 32-bit userspace? victor> Such test does exist and it is part of CI already, it is dubbed as MIPS multi-lib victor> tests where on top mips64 kernel tests are run for n64, n32, and o32 MIPS ABIs victor> user-land. victor> Note mips32 CI in question does cover kernel functionality for example victor> KLM build and check, SystemTap test, ltp and other kernel operations are tested. victor> I.e it does test 32 bit MIPS kernel as well, but user-land is involved in such victor> tests, and as it was described, it is slow compared to other qemu cases. Thanks, Victor And I guess maybe we should update our recommendations in the docs. Thoughts on this, Phil? r~ [*] Where it is now, it can't be used for gdb (mips_cpu_get_phys_page_debug). When used there, we should not modify cpu state, i.e. actually insert the PTE into the MIPS TLB, but we could still make use of the information available.