From: Kito Cheng <kito.ch...@sifive.com> Signed-off-by: Kito Cheng <kito.ch...@sifive.com> Signed-off-by: Frank Chang <frank.ch...@sifive.com> --- target/riscv/insn32-64.decode | 3 +++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvb.c.inc | 23 +++++++++++++++++ target/riscv/translate.c | 33 +++++++++++++++++++++++++ 4 files changed, 62 insertions(+)
diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 8e6ec4750f3..42bafbc03a0 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -104,6 +104,9 @@ rorw 0110000 .......... 101 ..... 0111011 @r rolw 0110000 .......... 001 ..... 0111011 @r grevw 0110100 .......... 101 ..... 0111011 @r gorcw 0010100 .......... 101 ..... 0111011 @r +sh1addu_w 0010000 .......... 010 ..... 0111011 @r +sh2addu_w 0010000 .......... 100 ..... 0111011 @r +sh3addu_w 0010000 .......... 110 ..... 0111011 @r sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 sbclriw 0100100 .......... 001 ..... 0011011 @sh5 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 76ba0698511..e23a378dec4 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -621,6 +621,9 @@ ror 0110000 .......... 101 ..... 0110011 @r rol 0110000 .......... 001 ..... 0110011 @r grev 0110100 .......... 101 ..... 0110011 @r gorc 0010100 .......... 101 ..... 0110011 @r +sh1add 0010000 .......... 010 ..... 0110011 @r +sh2add 0010000 .......... 100 ..... 0110011 @r +sh3add 0010000 .......... 110 ..... 0110011 @r sbseti 001010 ........... 001 ..... 0010011 @sh sbclri 010010 ........... 001 ..... 0010011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index eade85125c5..31d791236d9 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -246,6 +246,17 @@ static bool trans_gorci(DisasContext *ctx, arg_gorci *a) return gen_arith_shamt_tl(ctx, a, &gen_gorc); } +#define GEN_TRANS_SHADD(SHAMT) \ +static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \ +{ \ + REQUIRE_EXT(ctx, RVB); \ + return gen_arith(ctx, a, &gen_sh##SHAMT##add); \ +} + +GEN_TRANS_SHADD(1) +GEN_TRANS_SHADD(2) +GEN_TRANS_SHADD(3) + /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -411,4 +422,16 @@ static bool trans_gorciw(DisasContext *ctx, arg_gorciw *a) return gen_arith_shamt_tl(ctx, a, &gen_gorcw); } +#define GEN_TRANS_SHADDU_W(SHAMT) \ +static bool trans_sh##SHAMT##addu_w(DisasContext *ctx, \ + arg_sh##SHAMT##addu_w *a) \ +{ \ + REQUIRE_EXT(ctx, RVB); \ + return gen_arith(ctx, a, &gen_sh##SHAMT##addu_w); \ +} + +GEN_TRANS_SHADDU_W(1) +GEN_TRANS_SHADDU_W(2) +GEN_TRANS_SHADDU_W(3) + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 566e60d0d20..584550a9db2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -968,6 +968,21 @@ static void gen_gorc(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(shamt); } +#define GEN_SHADD(SHAMT) \ +static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t; \ + t = tcg_temp_new(); \ + \ + tcg_gen_shli_tl(t, arg1, SHAMT); \ + tcg_gen_add_tl(ret, t, arg2); \ + \ + tcg_temp_free(t); \ +} + +GEN_SHADD(1) +GEN_SHADD(2) +GEN_SHADD(3) #ifdef TARGET_RISCV64 @@ -1219,6 +1234,24 @@ static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2) tcg_temp_free(shamt); } +#define GEN_SHADDU_W(SHAMT) \ +static void gen_sh##SHAMT##addu_w(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t; \ + t = tcg_temp_new(); \ + \ + tcg_gen_ext32u_tl(t, arg1); \ + \ + tcg_gen_shli_tl(t, t, SHAMT); \ + tcg_gen_add_tl(ret, t, arg2); \ + \ + tcg_temp_free(t); \ +} + +GEN_SHADDU_W(1) +GEN_SHADDU_W(2) +GEN_SHADDU_W(3) + #endif static bool gen_arith(DisasContext *ctx, arg_r *a, -- 2.17.1