LSA and LDSA opcodes are also available with MIPS release 6.
Introduce the decodetree config files and call the decode()
helpers in the main decode_opc() loop.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/translate.h | 2 ++
target/mips/isa-mips32r6.decode | 17 ++++++++++++++
target/mips/isa-mips64r6.decode | 17 ++++++++++++++
target/mips/isa-mips_rel6_translate.c | 33 +++++++++++++++++++++++++++
target/mips/translate.c | 10 ++++++++
target/mips/meson.build | 3 +++
6 files changed, 82 insertions(+)
create mode 100644 target/mips/isa-mips32r6.decode
create mode 100644 target/mips/isa-mips64r6.decode
create mode 100644 target/mips/isa-mips_rel6_translate.c
diff --git a/target/mips/translate.h b/target/mips/translate.h
index 00601232b97..dcd8de602c1 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -96,8 +96,10 @@ extern TCGv bcond;
void msa_translate_init(void);
/* decodetree generated */
+bool decode_mips32r6(DisasContext *ctx, uint32_t insn);
bool decode_msa32(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64)
+bool decode_mips64r6(DisasContext *ctx, uint32_t insn);
bool decode_msa64(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode
new file mode 100644
index 00000000000..027585ee042
--- /dev/null
+++ b/target/mips/isa-mips32r6.decode
@@ -0,0 +1,17 @@
+# MIPS32 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS32 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06)
+#
+
+&lsa rd rt rs sa
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
+
+LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
diff --git a/target/mips/isa-mips64r6.decode b/target/mips/isa-mips64r6.decode
new file mode 100644
index 00000000000..e812224341e
--- /dev/null
+++ b/target/mips/isa-mips64r6.decode
@@ -0,0 +1,17 @@
+# MIPS64 Release 6 instruction set
+#
+# Copyright (C) 2020 Philippe Mathieu-Daudé
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# Reference:
+# MIPS Architecture for Programmers Volume II-A
+# The MIPS64 Instruction Set Reference Manual, Revision 6.06
+# (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
+#
+
+&lsa rd rt rs sa !extern
+
+@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &lsa
+
+DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
diff --git a/target/mips/isa-mips_rel6_translate.c
b/target/mips/isa-mips_rel6_translate.c
new file mode 100644
index 00000000000..c77f3ed57e0
--- /dev/null
+++ b/target/mips/isa-mips_rel6_translate.c
@@ -0,0 +1,33 @@
+/*
+ * MIPS emulation for QEMU - # Release 6 translation routines
+ *
+ * Copyright (c) 2004-2005 Jocelyn Mayer
+ * Copyright (c) 2006 Marius Groeger (FPU operations)
+ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support)
+ * Copyright (c) 2020 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder. */
+#include "decode-isa-mips32r6.c.inc"
+#if defined(TARGET_MIPS64)
+#include "decode-isa-mips64r6.c.inc"
+#endif /* TARGET_MIPS64 */
+
+static bool trans_LSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_LSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+
+#if defined(TARGET_MIPS64)
+static bool trans_DLSA(DisasContext *ctx, arg_LSA *a)
+{
+ return gen_DLSA(ctx, a->rd, a->rt, a->rs, a->sa);
+}
+#endif /* TARGET_MIPS64 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index b3c45d6211a..9b333f97822 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28320,6 +28320,16 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
return;
}
+ /* ISA */
+#if defined(TARGET_MIPS64)
+ if ((ctx->insn_flags & ISA_MIPS64R6) && decode_mips64r6(ctx, ctx->opcode))
{
+ return;
+ }
+#endif /* TARGET_MIPS64 */
+ if ((ctx->insn_flags & ISA_MIPS32R6) && decode_mips32r6(ctx, ctx->opcode))
{
+ return;
+ }
+
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
diff --git a/target/mips/meson.build b/target/mips/meson.build
index 124b5f7d49d..a459d0917ee 100644
--- a/target/mips/meson.build
+++ b/target/mips/meson.build
@@ -1,7 +1,9 @@
gen = [
+ decodetree.process('isa-mips32r6.decode', extra_args: [
'--decode=decode_mips32r6' ]),
decodetree.process('mod-msa32.decode', extra_args: [ '--decode=decode_msa32'
]),
]
gen64 = [
+ decodetree.process('isa-mips64r6.decode', extra_args: [
'--decode=decode_mips64r6' ]),
decodetree.process('mod-msa64.decode', extra_args: [ '--decode=decode_msa64'
]),
]
@@ -13,6 +15,7 @@
'fpu_helper.c',
'gdbstub.c',
'helper.c',
+ 'isa-mips_rel6_translate.c',
'lmmi_helper.c',
'op_helper.c',
'mod-msa_helper.c',
--
2.26.2
