Missed in previous "Convert MSA to decodetree" series.
Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org>
---
target/mips/translate.h | 8 +++++++-
target/mips/translate.c | 4 ++--
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.h b/target/mips/translate.h
index cba28f49753..da88387418c 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -55,11 +55,15 @@ typedef struct DisasContext {
void generate_exception_end(DisasContext *ctx, int excp);
void gen_reserved_instruction(DisasContext *ctx);
void check_insn(DisasContext *ctx, uint64_t flags);
-void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
+#ifdef TARGET_MIPS64
+void check_mips_64(DisasContext *ctx);
+#endif
+void gen_base_offset_addr(DisasContext *ctx, TCGv addr, int base, int offset);
void gen_load_gpr(TCGv t, int reg);
void gen_store_gpr(TCGv t, int reg);
+extern TCGv cpu_gpr[32], cpu_PC;
extern TCGv bcond;
#define LOG_DISAS(...) \
@@ -82,6 +86,8 @@ extern TCGv bcond;
/* MSA */
void msa_translate_init(void);
+
+/* decodetree generated */
bool decode_msa32(DisasContext *ctx, uint32_t insn);
#endif
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 41c0b59a473..3c7307233c9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2187,7 +2187,7 @@ enum {
};
/* global register indices */
-static TCGv cpu_gpr[32], cpu_PC;
+TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
static TCGv cpu_dspctrl, btarget;
TCGv bcond;
@@ -2728,7 +2728,7 @@ static inline void check_ps(DisasContext *ctx)
* This code generates a "reserved instruction" exception if 64-bit
* instructions are not enabled.
*/
-static inline void check_mips_64(DisasContext *ctx)
+void check_mips_64(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) {
generate_exception_end(ctx, EXCP_RI);
--
2.26.2
