LWL/LWR/SWL/SWR opcodes have been removed from the Release 6. Add a single decodetree entry for the opcodes, triggering Reserved Instruction if ever used.
Remove unreachable check_insn_opc_removed() calls. Signed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> --- target/mips/isa-mips32r6.decode | 5 +++++ target/mips/translate.c | 5 +---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/mips/isa-mips32r6.decode b/target/mips/isa-mips32r6.decode index e3b3934539a..89a0085fafd 100644 --- a/target/mips/isa-mips32r6.decode +++ b/target/mips/isa-mips32r6.decode @@ -20,5 +20,10 @@ REMOVED 010011 ----- ----- ----- ----- ------ # COP1X (COP3) REMOVED 011100 ----- ----- ----- ----- ------ # SPECIAL2 +REMOVED 100010 ----- ----- ---------------- # LWL +REMOVED 100110 ----- ----- ---------------- # LWR +REMOVED 101010 ----- ----- ---------------- # SWL +REMOVED 101110 ----- ----- ---------------- # SWR + REMOVED 101111 ----- ----- ---------------- # CACHE REMOVED 110011 ----- ----- ---------------- # PREF diff --git a/target/mips/translate.c b/target/mips/translate.c index ba1b2360c50..3d627d049bd 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -28636,11 +28636,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (ctx->insn_flags & INSN_R5900) { check_insn_opc_user_only(ctx, INSN_R5900); } + check_insn_opc_removed(ctx, ISA_MIPS32R6); /* Fallthrough */ case OPC_LWL: case OPC_LWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); - /* Fallthrough */ case OPC_LB: case OPC_LH: case OPC_LW: @@ -28651,8 +28650,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; case OPC_SWL: case OPC_SWR: - check_insn_opc_removed(ctx, ISA_MIPS32R6); - /* fall through */ case OPC_SB: case OPC_SH: case OPC_SW: -- 2.26.2