On 1/8/21 11:51 AM, Peter Maydell wrote:
> In commit cd8be50e58f63413c0 we converted the A32 coprocessor
> insns to decodetree. This accidentally broke XScale/iWMMXt insns,
> because it moved the handling of "cp insns which are handled
> by looking up the cp register in the hashtable" from after the
> call to the legacy disas_xscale_insn() decode to before it,
> with the result that all XScale/iWMMXt insns now UNDEF.
>
> Update valid_cp() so that it knows that on XScale cp 0 and 1
> are not standard coprocessor instructions; this will cause
> the decodetree trans_ functions to ignore them, so that
> execution will correctly get through to the legacy decode again.
>
> Cc: qemu-sta...@nongnu.org
> Reported-by: Guenter Roeck <li...@roeck-us.net>
> Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
> ---
> With this Guenter's test image now successfully boots
> and shuts down again.
> ---
Thanks a lot for the fix!
Tested-by: Guenter Roeck <li...@roeck-us.net>
> target/arm/translate.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index f5acd32e76a..528b93dffa2 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -5282,7 +5282,14 @@ static bool valid_cp(DisasContext *s, int cp)
> * only cp14 and cp15 are valid, and other values aren't considered
> * to be in the coprocessor-instruction space at all. v8M still
> * permits coprocessors 0..7.
> + * For XScale, we must not decode the XScale cp0, cp1 space as
> + * a standard coprocessor insn, because we want to fall through to
> + * the legacy disas_xscale_insn() decoder after decodetree is done.
> */
> + if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
> + return false;
> + }
> +
> if (arm_dc_feature(s, ARM_FEATURE_V8) &&
> !arm_dc_feature(s, ARM_FEATURE_M)) {
> return cp >= 14;
>
