On Mon, 22 Mar 2021 at 14:10, Peter Maydell <peter.mayd...@linaro.org> wrote:
>
> On Sat, 20 Mar 2021 at 00:06, Richard Henderson
> <richard.hender...@linaro.org> wrote:
> >
> > Pretend the fault always happens at page table level 3.
> >
> > Failure to set this leaves level = 0, which is impossible for
> > ARMFault_Permission, and produces an invalid syndrome, which
> > reaches g_assert_not_reached in cpu_loop.
> >
> > Fixes: 8db94ab4e5db ("linux-user/aarch64: Pass syndrome to EXC_*_ABORT")
> > Reported-by: Laurent Vivier <laur...@vivier.eu>
> > Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> > ---
> > target/arm/tlb_helper.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
> > index 9609333cbd..3107f9823e 100644
> > --- a/target/arm/tlb_helper.c
> > +++ b/target/arm/tlb_helper.c
> > @@ -163,6 +163,7 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int
> > size,
> > } else {
> > fi.type = ARMFault_Translation;
> > }
> > + fi.level = 3;
> >
> > /* now we have a real cpu fault */
> > cpu_restore_state(cs, retaddr, true);
>
>
> Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
...and applied to target-arm.next.
thanks
-- PMM
