On Tue, 23 Mar 2021 at 01:59, Alistair Francis <alistair.fran...@wdc.com> wrote: > > The following changes since commit c95bd5ff1660883d15ad6e0005e4c8571604f51a: > > Merge remote-tracking branch 'remotes/philmd/tags/mips-fixes-20210322' into > staging (2021-03-22 14:26:13 +0000) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210322-2 > > for you to fetch changes up to 9a27f69bd668d9d71674407badc412ce1231c7d5: > > target/riscv: Prevent lost illegal instruction exceptions (2021-03-22 > 21:54:40 -0400) > > ---------------------------------------------------------------- > RISC-V PR for 6.0 > > This PR includes: > - Fix for vector CSR access > - Improvements to the Ibex UART device > - PMP improvements and bug fixes > - Hypervisor extension bug fixes > - ramfb support for the virt machine > - Fast read support for SST flash > - Improvements to the microchip_pfsoc machine
Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.0 for any user-visible changes. -- PMM
