> > > > In fact these aren't problems. The packet may be sent or data > > written, as long as they aren't corrupted. A device is allowed to > > "delay" a reset (but not indefinitely). > > Oh, but corruption could easily happen. Consider for example a disk > controller waiting for DMA ready signal a device separate from the > DMA > controller. Due to reset glitches in the device or signal chain, the > DMA ready signal arrives but the DMA controller still contains old > information, writing the data to disk from wrong memory location.
Would not this corruption also happen on real hardware? If reset to the disk controller is delayed by a slow gate or extra capacitance on a line?
