On 5/21/21 10:25 AM, Matheus K. Ferst wrote:
On 18/05/2021 07:12, Richard Henderson wrote:
On 5/17/21 3:50 PM, matheus.fe...@eldorado.org.br wrote:
+ if(a->l && (ctx->insns_flags & PPC_64B)) {
Space after IF.
> If I look back to the 6xx manual, I see
NOTE: If L = 1, the instruction form is invalid.
The fact that we're allowing L=1 for ppc32 is an existing bug, afaics. We
should fix that.
r~
The previous commit on this line in translate.c says that "on most 32bit CPUs
we should always treat the compare as 32bit compare, as the CPU will ignore the
L bit", so maybe it was intentional. Should we change it anyway?
The actual change of 36f48d9c78c is about NARROW_MODE, which is about the
MSR.SF bit, and is correct.
The commit message mentions the e500mc specifically does check the L bit, and
then hand-waves about the others not checking. But the text I found in the 6xx
manual says that one checks too.
I wonder if the IBM folk can shed any further light on this?
r~
