Hi Philippe,
On 5/29/21 3:52 PM, Philippe Mathieu-Daudé wrote:
> I think this opcode never worked correctly.
>
> Per the "MIPS® Architecture Extension: nanoMIPS32 DSP Technical
> Reference Manual — Revision 0.04" p. 88 "BPOSGE32C":
>
> "First, the offset argument is left-shifted by one bit to form
> a 17-bit signed integer value."
>
> The caller, decode_nanomips_32_48_opc(), doesn't shift the offset:
>
> case NM_BPOSGE32C:
> check_dsp_r3(ctx);
> {
> int32_t imm = extract32(ctx->opcode, 1, 13) |
> extract32(ctx->opcode, 0, 1) << 13;
>
> gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2,
> imm);
> }
> break;
You're right. We will prepare a patch very soon.
-- Aleksandar R.
