From: Claudio Fontana <cfont...@suse.de> restrict zcr_el1, zcr_el2, zcr_no_el2, zcr_el3 reginfo, and the related SVE functions to TARGET_AARCH64.
Signed-off-by: Claudio Fontana <cfont...@suse.de> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Alex Bennée <alex.ben...@linaro.org> --- target/arm/tcg/cpregs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c index 8422da4335..56d56f7f81 100644 --- a/target/arm/tcg/cpregs.c +++ b/target/arm/tcg/cpregs.c @@ -5791,6 +5791,8 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = { REGINFO_SENTINEL }; +#ifdef TARGET_AARCH64 + static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5843,6 +5845,8 @@ static const ARMCPRegInfo zcr_el3_reginfo = { .writefn = zcr_write, .raw_writefn = raw_write }; +#endif /* TARGET_AARCH64 */ + static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -7572,6 +7576,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vhe_reginfo); } +#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); if (arm_feature(env, ARM_FEATURE_EL2)) { @@ -7584,7 +7589,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } -#ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); } @@ -7614,7 +7618,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } -#endif +#endif /* TARGET_AARCH64 */ if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); -- 2.20.1