LIU Zhiwei <zhiwei_...@c-sky.com> 於 2021年4月9日 週五 下午3:52寫道：
> The xtvt WARL XLEN-bit CSR holds the base address of the trap vector table,
> aligned on a 64-byte or greater power-of-two boundary.
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
> ---
> target/riscv/cpu.h | 2 ++
> target/riscv/cpu_bits.h | 2 ++
> target/riscv/csr.c | 28 ++++++++++++++++++++++++++++
> 3 files changed, 32 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9e389d7bbf..b5fd796f98 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -173,11 +173,13 @@ struct CPURISCVState {
> target_ulong medeleg;
>
> target_ulong stvec;
> + target_ulong stvt; /* clic-spec */
> target_ulong sepc;
> target_ulong scause;
> target_ulong sintthresh; /* clic-spec */
>
> target_ulong mtvec;
> + target_ulong mtvt; /* clic-spec */
> target_ulong mepc;
> target_ulong mcause;
> target_ulong mtval; /* since: priv-1.10.0 */
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 9447801d22..7922097776 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -149,6 +149,7 @@
> #define CSR_MIE 0x304
> #define CSR_MTVEC 0x305
> #define CSR_MCOUNTEREN 0x306
> +#define CSR_MTVT 0x307 /* clic-spec-draft */
>
> /* 32-bit only */
> #define CSR_MSTATUSH 0x310
> @@ -178,6 +179,7 @@
> #define CSR_SIE 0x104
> #define CSR_STVEC 0x105
> #define CSR_SCOUNTEREN 0x106
> +#define CSR_STVT 0x107 /* clic-spec-draft */
>
> /* Supervisor Trap Handling */
> #define CSR_SSCRATCH 0x140
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 39ff72041a..e12222b77f 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -667,6 +667,18 @@ static int write_mcounteren(CPURISCVState *env, int
> csrno, target_ulong val)
> return 0;
> }
>
> +static int read_mtvt(CPURISCVState *env, int csrno, target_ulong *val)
> +{
> + *val = env->mtvt;
> + return 0;
> +}
> +
> +static int write_mtvt(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + env->mtvt = val & ~((1ULL << 6) - 1);
>
mtvt CSR has additional minimum alignment restriction in v0.8 CLIC spec[1]:
2^ceiling(log2(N)) x 4 bytes, where N is the maximum number of interrupt
sources.
> + return 0;
> +}
> +
> /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
> static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong
> *val)
> {
> @@ -876,6 +888,18 @@ static int write_scounteren(CPURISCVState *env, int
> csrno, target_ulong val)
> return 0;
> }
>
> +static int read_stvt(CPURISCVState *env, int csrno, target_ulong *val)
stvt CSR seems not to exist in v0.8 CLIC spec[1].
[1] https://github.com/riscv/riscv-fast-interrupt/blob/74f86c3858/clic.adoc
Regards,
Frank Chang
>
+{
> + *val = env->stvt;
> + return 0;
> +}
> +
> +static int write_stvt(CPURISCVState *env, int csrno, target_ulong val)
> +{
> + env->stvt = val & ~((1ULL << 6) - 1);
> + return 0;
> +}
> +
> /* Supervisor Trap Handling */
> static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
> {
> @@ -1730,6 +1754,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32, read_zero },
>
> /* Machine Mode Core Level Interrupt Controller */
> + [CSR_MTVT] = { "mtvt", clic, read_mtvt, write_mtvt },
> [CSR_MINTSTATUS] = { "mintstatus", clic, read_mintstatus },
> [CSR_MINTTHRESH] = { "mintthresh", clic, read_mintthresh,
> write_mintthresh },
> @@ -1739,5 +1764,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> [CSR_SINTTHRESH] = { "sintthresh", clic, read_sintthresh,
> write_sintthresh },
>
> + /* Supervisor Mode Core Level Interrupt Controller */
> + [CSR_STVT] = { "stvt", clic, read_stvt, write_stvt },
> +
> #endif /* !CONFIG_USER_ONLY */
> };
> --
> 2.25.1
>
>
>
