LIU Zhiwei <zhiwei_...@c-sky.com> 於 2021年4月9日 週五 下午3:58寫道：
> This patch set gives an implementation of "RISC-V Core-Local Interrupt > Controller(CLIC) Version 0.9-draft-20210217". It comes from [1], where > you can find the pdf format or the source code. > > I take over the job from Michael Clark, who gave the first implementation > of clic-v0.7 specification. If there is any copyright question, please > let me know. > > Features: > 1. support four kinds of trigger types. > 2. Preserve the CSR WARL/WPRI semantics. > 3. Option to select different modes, such as M/S/U or M/U. > 4. At most 4096 interrupts. > 5. At most 1024 apertures. > > Todo: > 1. Encode the interrupt trigger information to exccode. > 2. Support complete CSR mclicbase when its number is fixed. > 3. Gave each aperture an independend address. > > It have passed my qtest case and freertos test. Welcome to have a try > for your hardware. > > Any advice is welcomed. Thanks very much. > > Zhiwei > > [1] specification website: https://github.com/riscv/riscv-fast-interrupt. > [2] Michael Clark origin work: > https://github.com/sifive/riscv-qemu/tree/sifive-clic. > > > LIU Zhiwei (11): > target/riscv: Add CLIC CSR mintstatus > target/riscv: Update CSR xintthresh in CLIC mode > hw/intc: Add CLIC device > target/riscv: Update CSR xie in CLIC mode > target/riscv: Update CSR xip in CLIC mode > target/riscv: Update CSR xtvec in CLIC mode > target/riscv: Update CSR xtvt in CLIC mode > target/riscv: Update CSR xnxti in CLIC mode > target/riscv: Update CSR mclicbase in CLIC mode > target/riscv: Update interrupt handling in CLIC mode > target/riscv: Update interrupt return in CLIC mode > > default-configs/devices/riscv32-softmmu.mak | 1 + > default-configs/devices/riscv64-softmmu.mak | 1 + > hw/intc/Kconfig | 3 + > hw/intc/meson.build | 1 + > hw/intc/riscv_clic.c | 836 ++++++++++++++++++++ > include/hw/intc/riscv_clic.h | 103 +++ > target/riscv/cpu.h | 9 + > target/riscv/cpu_bits.h | 32 + > target/riscv/cpu_helper.c | 117 ++- > target/riscv/csr.c | 247 +++++- > target/riscv/op_helper.c | 25 + > 11 files changed, 1363 insertions(+), 12 deletions(-) > create mode 100644 hw/intc/riscv_clic.c > create mode 100644 include/hw/intc/riscv_clic.h > > -- > 2.25.1 > > > After reviewing this patchset. I found that CLIC v0.8 spec is quite incomplete. It lacks all S-mode related CSRs. If you think that it's just the v0.8 spec issue for not covering all the required S-mode related CSRs -- and we should include them in CLIC v0.8 implementation even it's not documented explicitly. You can just ignore my comments in regard to S-mode CSRs for v0.8 CLIC. (Besides mintthresh, v0.8 spec does say that it holds the 8-bit field interrupt thresholds for each privilege mode.) Regards, Frank Chang
