Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines

[Philippe Mathieu-Daudé]

On 7/9/21 5:30 AM, Alistair Francis wrote:
> Expose the 12 interrupt pending bits in MIP as GPIO lines.
> 
> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com>
> ---
>  target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)

Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>