Re: [PATCH v1 1/5] target/riscv: Expose interrupt pending bits as GPIO lines

[Richard Henderson]

On 7/8/21 8:30 PM, Alistair Francis wrote:

Expose the 12 interrupt pending bits in MIP as GPIO lines.

Signed-off-by: Alistair Francis<alistair.fran...@wdc.com>
---
  target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++
  1 file changed, 30 insertions(+)

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>

r~