Hello Philippe,
Le 30/08/2021 à 23:40, Philippe Mathieu-Daudé a écrit :
> On 8/30/21 11:38 PM, Philippe Mathieu-Daudé wrote:
>> On 8/30/21 7:16 PM, Frédéric Pétrot wrote:
>>> Adding the support for the 128-bit arithmetic and logic instructions.
>>> Remember that all (i) instructions are now acting on 128-bit registers, that
>>> a few others are added to cope with values that are held on 64 bits within
>>> the 128-bit registers, and that the ones that cope with values on 32-bit
>>> must also be modified for proper sign extension.
>>> Most algorithms taken from Hackers' delight.
>>>
>>> Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr>
>>> Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org>
>>> ---
>>> target/riscv/insn32.decode | 13 +
>>> target/riscv/insn_trans/trans_rvi.c.inc | 955 +++++++++++++++++++++++-
>>> target/riscv/translate.c | 25 +
>>> 3 files changed, 976 insertions(+), 17 deletions(-)
>>
>>> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
>>> b/target/riscv/insn_trans/trans_rvi.c.inc
>>> index 772330a766..0401ba3d69 100644
>>> --- a/target/riscv/insn_trans/trans_rvi.c.inc
>>> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
>>> @@ -26,14 +26,20 @@ static bool trans_illegal(DisasContext *ctx, arg_empty
>>> *a)
>>>
>>> static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
>>> {
>>> - REQUIRE_64BIT(ctx);
>>> - return trans_illegal(ctx, a);
>>> + REQUIRE_64_OR_128BIT(ctx);
>>> + return trans_illegal(ctx, a);
>>> }
>>>
>>> static bool trans_lui(DisasContext *ctx, arg_lui *a)
>>> {
>>> if (a->rd != 0) {
>>> tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
>>> +#if defined(TARGET_RISCV128)
>>> + if (is_128bit(ctx)) {
>>
>> Maybe this could allow the compiler eventually elide the
>> code and avoid superfluous #ifdef'ry:
>>
>> if (TARGET_LONG_BITS >= 128) {
>
> Actually:
>
> if (TARGET_LONG_BITS >= 128 && is_128bit(ctx)) {
We may have taken a wrong path then, because we have kept
TARGET_LONG_BITS == 64 for the 128-bit case (as we use the tcg_xxx_tl of the
64 version to generate our micro-ops, which I admit might be a mistake).
Frédéric
>
>>
>>> + tcg_gen_ext_i64_i128(cpu_gpr[a->rd], cpu_gprh[a->rd],
>>> + cpu_gpr[a->rd]);
>>> + }
>>> +#endif
>>> }
>>> return true;
>>> }
>>
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.pet...@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
