[PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

[frank . chang]

From: Frank Chang <frank.ch...@sifive.com>

Signed-off-by: Frank Chang <frank.ch...@sifive.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
---
 target/riscv/csr.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 127393eb956..9f51626a3d8 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -297,10 +297,11 @@ static RISCVException write_vxrm(CPURISCVState *env, int 
csrno,
                                  target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
+    target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
     if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
-    env->mstatus |= MSTATUS_VS;
+    env->mstatus |= MSTATUS_VS | sd;
 #endif
 
     env->vxrm = val;
@@ -318,10 +319,11 @@ static RISCVException write_vxsat(CPURISCVState *env, int 
csrno,
                                   target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
+    target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
     if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
-    env->mstatus |= MSTATUS_VS;
+    env->mstatus |= MSTATUS_VS | sd;
 #endif
 
     env->vxsat = val;
@@ -339,10 +341,11 @@ static RISCVException write_vstart(CPURISCVState *env, 
int csrno,
                                    target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
+    target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
     if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
-    env->mstatus |= MSTATUS_VS;
+    env->mstatus |= MSTATUS_VS | sd;
 #endif
 
     /*
@@ -362,10 +365,11 @@ static int read_vcsr(CPURISCVState *env, int csrno, 
target_ulong *val)
 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
 {
 #if !defined(CONFIG_USER_ONLY)
+    target_ulong sd = riscv_cpu_is_32bit(env) ? MSTATUS32_SD : MSTATUS64_SD;
     if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
         return RISCV_EXCP_ILLEGAL_INST;
     }
-    env->mstatus |= MSTATUS_VS;
+    env->mstatus |= MSTATUS_VS | sd;
 #endif
 
     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
-- 
2.25.1