On Mon, Oct 18, 2021 at 4:09 PM Frank Chang <frank.ch...@sifive.com> wrote: > > On Mon, Oct 18, 2021 at 2:00 PM Alistair Francis <alistai...@gmail.com> wrote: >> >> On Fri, Oct 15, 2021 at 5:48 PM <frank.ch...@sifive.com> wrote: >> > >> > From: Frank Chang <frank.ch...@sifive.com> >> > >> > This patchset implements the vector extension v1.0 for RISC-V on QEMU. >> > >> > RVV v1.0 spec is now fronzen for public review: >> > https://github.com/riscv/riscv-v-spec/releases/tag/v1.0 >> > >> > The port is available here: >> > https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v8 >> > >> > RVV v1.0 can be enabled with -cpu option: v=true and specify vext_spec >> > option to v1.0 (i.e. vext_spec=v1.0) >> >> It doesn't seem like this series made it to the general QEMU list. You >> might want to check to see what happened there. >> > > Hi Alistair, what does "general QEMU list" mean here?
To the qemu-devel mailing list. A good way to check is to have a look at something like patchew (https://patchew.org/QEMU/) and see if the patches are there. Alistair