On 12/13/21 1:02 PM, Alex Bennée wrote:
+ cpu->midr = 0x410fc0f1;
hmm wikipedia lists the part number as 0xc05 (and the a15 as 0xc0f) but
I can't find the actual value in the TRM.
https://developer.arm.com/documentation/ddi0434/c
has exactly this value at the top of table 4-9.
+ cpu->reset_fpsid = 0x41023051;
I think for the a5 the FPU is optional so maybe we need a cpu option
here? Or maybe just assume it's enabled on QEMUs version?
Yeah, there's no entry for fpsid in the above manual.
+ cpu->isar.id_mmfr0 = 0x00100103;
the TRM says [11:8] Outermost shareability 0x0 L1 cache coherency not supported.
Again, this does match table 4-9.
r~
