From: Fabiano Rosas <faro...@linux.ibm.com>
The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
just a clean copy of the MSR.
We're using the BookE Exception Syndrome Register which is different
from the 405.
Signed-off-by: Fabiano Rosas <faro...@linux.ibm.com>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
[ clg: restored SPR_40x_ESR settings ]
Message-Id: <20220118184448.852996-14-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
target/ppc/excp_helper.c | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7d89bd0651d8..b528457d9298 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -483,30 +483,19 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
env->error_code = 0;
return;
}
-
- /*
- * FP exceptions always have NIP pointing to the faulting
- * instruction, so always use store_next and claim we are
- * precise in the MSR.
- */
- msr |= 0x00100000;
- env->spr[SPR_BOOKE_ESR] = ESR_FP;
+ env->spr[SPR_40x_ESR] = ESR_FP;
break;
case POWERPC_EXCP_INVAL:
trace_ppc_excp_inval(env->nip);
- msr |= 0x00080000;
- env->spr[SPR_BOOKE_ESR] = ESR_PIL;
+ env->spr[SPR_40x_ESR] = ESR_PIL;
break;
case POWERPC_EXCP_PRIV:
- msr |= 0x00040000;
- env->spr[SPR_BOOKE_ESR] = ESR_PPR;
+ env->spr[SPR_40x_ESR] = ESR_PPR;
break;
case POWERPC_EXCP_TRAP:
- msr |= 0x00020000;
- env->spr[SPR_BOOKE_ESR] = ESR_PTR;
+ env->spr[SPR_40x_ESR] = ESR_PTR;
break;
default:
- /* Should never occur */
cpu_abort(cs, "Invalid program exception %d. Aborting\n",
env->error_code);
break;
--
2.34.1
